The present invention generally relates to semiconductor devices and more particularly to a semiconductor structure that facilitates fabrication of a semiconductor integrated circuit with reduced number of fabrication steps while maintaining a reliable electrical contact at contact holes.
A DRAM (Dynamic Random Access Memory) is a high speed, volatile semiconductor memory device that stores information in a capacitor in the form of electric charges and is generally provided in the form of an integrated circuit. Thus, a DRAM integrated circuit includes a number of memory cells each formed of a memory cell capacitor and a cooperating memory cell transistor, in a state that the memory cells are integrated monolithically on a semiconductor substrate. As each of the memory cells has a simple structure, DRAM is particularly suitable for realizing a high integration density by way of miniaturization of the individual memory cells.
However, the attempt to realize a very large capacity DRAM, of which storage capacity reaches 1 Gbit or more, has revealed a problem that the capacitance of the memory cell capacitors becomes to small for a proper operation of the DRAM as a result of the excessive device miniaturization. In order to avoid this problem, various proposals are made so far.
For example, the U.S. Pat. No. 5,414,636 describes a DRAM structure that uses a stacked-fin type capacitor for the memory cell capacitor. By using the stacked-fin type capacitor, in which a number of electrode fins are stacked, it is possible to compensate for the decrease of the total area of the memory cell capacitor caused as a result of the device miniaturization.
However, such an attempt is successful only for those devices of which storage capacity is smaller than 256 Mbits. In order to realize a storage capacity of 256 Mbits or more, it is inevitable to increase the height of the memory cell capacitor, even when the stacked-fin type capacitor is used for the memory cell capacitor. However, such an increase in the height of the memory cell capacitor causes a difficulty of proper focusing at the time of exposure of minute patterns or contact holes, due to the undesirable formation of a step structure between a memory cell region of the DRAM, where the memory cells are formed, and a peripheral region where peripheral circuits of the DRAM are formed. It should be noted that an exposure of deep contact hole is essential for the fabrication of a DRAM of the stacked-fin type, while such an exposure of a deep contact hole by way of a high-resolution optical system is extremely difficult. A high-resolution optical system characteristically has a very small focal depth.
In order to overcome the foregoing difficulty, there is proposed a DRAM structure in the Japanese Laid-open Patent Publication 8-274278 corresponding to the United States patent application Ser. No. 08/592,481, in which a minute contact hole is formed in correspondence to a drain region of a memory cell transistor by a self-alignment process. In the proposed structure, a cylindrical electrode of a memory capacitor establishes an electrical contact with the drain region at such a minute contact hole. The cylindrical capacitor electrode, in turn, extends through a through-hole formed in an interlayer insulation film that covers the memory cell transistor in an upward direction away from a semiconductor substrate. As the through-hole thus formed has a diameter substantially larger than a diameter of the foregoing minute contact hole, the problem of severe alignment is successfully avoided when exposing the through-hole. For example, the exposure of the through-hole can be achieved successfully by using a low resolution optical system having a large focal depth.
FIG. 1 shows the construction of a conventional DRAM memory cell 10 disclosed in the foregoing Japanese Laid-open Patent Publication 8-274278, which is incorporated herein as a reference.
Referring to FIG. 10, the memory cell 10 includes a memory cell transistor on an active region 11B of a Si substrate 11, wherein the active region 11B is defined on a surface of the Si substrate 11 by a field oxide film 11A as usual. The memory cell transistor, in turn, includes a polysilicon gate pattern 13 provided on a gate oxide film 12 in the foregoing active region 11B, wherein the polysilicon gate pattern 13 forms a part of a word line WL as usual. Further, the substrate 11 is formed with diffusion regions 11C and 11D at both sides of a channel region CH formed in the active region 11B in correspondence to the gate pattern 13, as a source and a drain of the memory cell transistor. As usual, the diffusion regions 11C and 11D are formed in a self-alignment process that uses the gate pattern 13 as a mask.
In the structure of FIG. 1, the polysilicon gate pattern 13 is covered, at a top surface and both side walls thereof, with an insulation film 13C in conformity with a cross-sectional shape of the gate pattern 13. Thus, there are formed an opening (11C).sub.C and another opening (11D).sub.C respectively exposing the source region 11C and the drain region 1D, wherein it should be noted that each of the openings (11C).sub.C and (11D).sub.C is formed between a pair of adjacent gate patterns 13 automatically in a self-aligned process.
On the structure including the self-aligned openings (11C).sub.C and (11D).sub.C thus formed, a thin SiN film 14 and a thick interlayer insulation film 15 are deposited consecutively. Further, a through-holes 15A is formed in the interlayer insulation film 15 by an RIE process in correspondence to each of the foregoing diffusion regions 11C and 11D. Each of the through-holes 15A thus formed exposes, at a bottom part thereof, the SiN film 14 that contacts directly with the diffusion region 11C or the diffusion region 11D via the foregoing opening (11C).sub.C or (11D).sub.C.
The SiN film 14 thus exposed is subsequently removed by an etching process, and a polysilicon film 16 is deposited on the inner surface of each of the through-holes 15A such that the polysilicon film 16 extends along the through-hole 15A and contacts with the exposed diffusion region 11C or 11D.
Further, a thin dielectric film 17 of Ta.sub.2 O.sub.5 of (Ba, Sr)TiO.sub.3 is deposited on the foregoing polysilicon film 16, and an inner space defined by the polysilicon film 16 is filled with a polysilicon column 18.
It should be noted that the polysilicon column 18 formed in correspondence to the drain region 11D projects beyond the top surface of the interlayer insulation film 15 and is covered by an insulation film 19. On the other hand, the polysilicon column 18 corresponding to the source region 11C carries thereon a bit line 20. The bit line 20 thereby contact with the source region 11C electrically via the polysilicon film 16 corresponding to the foregoing polysilicon column 18. In other words, the polysilicon film 16 corresponding to the source region 11C acts as a bit line contact structure L that connects the source region 11C to the bit line 20.
On the other hand, the polysilicon film 16 contacting with the drain region 11D forms a memory cell capacitor C together with the dielectric film 17 and the polysilicon column 18.
In the memory cell 10 of FIG. 1, it should be noted that the openings (11C).sub.C and (11D).sub.C are formed in a self-aligned process, without using a mask. In other words, the formation of the openings (11C).sub.C and (11D).sub.C can be achieved without taking into consideration the alignment error at the time of the mask process, and the size of the openings (11C).sub.C and (11D.sub.C can be reduced as desired. Further, the elimination of the mask process increases the throughput of fabrication of the device significantly. In addition, the formation of the electrode 20 on the planarized top surface of the interlayer insulation film 15 facilitates the submicron patterning of the interconnection pattern connected to the electrode 20.
On the other hand, the construction of FIG. 1 has a drawback in that the area of contact between the polysilicon film 16 forming the bit line contact structure L and the bit line pattern 20 is limited substantially. In other words, the structure of FIG. 1 suffers from the problem of increased resistance of the bit line contact structure L.
A similar problem occurs also in a general semiconductor device as long as the desired electrical contact is achieved by a contact hole that carries a thin conductive film such as an amorphous silicon film or a polysilicon film on a bottom surface as well as an inner surface of the contact hole.
FIGS. 2A-2C show the process of forming such a general contact hole.
Referring to FIG. 2A, an insulation film 2 of SiO.sub.2 or BPSG (borophosphosilicate glass) is provided on a Si substrate 1 in which a diffusion region 1A is formed. Further, a contact hole 2A is formed in the Si substrate 1 so as to expose the diffusion region 1A, and a conductive film 3 of amorphous silicon or polysilicon is deposited on the contact hole 2A by a CVD process such that the conductive film 3 covers the bottom surface as well as the side wall of the contact hole 2A. Thus, the conductive film 3 establishes a two-dimensional contact with the diffusion region 1A at the bottom of the contact hole 2A.
Next, the conductive film 2 is removed for the part deposited above the insulation film 2 by a CMP (chemical mechanical polishing) process as indicated in FIG. 2A, and an SiO.sub.2 film 4 is deposited on the structure thus obtained as indicated in FIG. 2B. As will be seen in FIG. 2B, the SiO.sub.2 film 4 fills the depression formed inside the conductive film 3 in correspondence to the contact hole 2A.
Next, in the step of FIG. 2C, the SiO.sub.2 film 4 is formed with an opening 4 so as to expose the top edge of the conductive film 3, and a conductive polysilicon electrode pattern 5 is deposited on the SiO.sub.2 film 4 so as to include the foregoing opening 4A.
In the contact structure of FIG. 2C, it should be noted that the contact between the conductive film 3 and the electrode pattern 5 is limited to a circled region indicated in FIG. 2C. Thus, the contact structure of FIG. 2C inevitably suffers from the problem of increased contact resistance caused by a limited contact area.